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altifigence-npu-full-v003

altifigence-npu-full-v002

altifigence-npu-full-v001

rtl

41module CVO_top (

// The sub_emax bf16_add (align + 25-bit add + normalize) is the integrated worst

// path; even after the 1a/1b split the align+add cones were too long.

// Barrel-shift align and the 25-bit add are now separated by their own register

// (sa0 holds the sign-extended aligned operands). Latency +1, bit-identical.

bf16_t sa_a_wire, sa_b_wire;

logic [7:0] sa_emax_wire;

logic [23:0] sa_aa_wire, sa_bb_wire;

always_comb begin : comb_sub_emax_align

sa_a_wire = to_bf16(in_data_s0);

sa_b_wire = bf16_t'({~in_emax_s0[15], in_emax_s0[14:0]}); // -emax

sa_emax_wire = (sa_a_wire.exp > sa_b_wire.exp) ? sa_a_wire.exp : sa_b_wire.exp;

sa_aa_wire = align_to_emax(sa_a_wire, sa_emax_wire);

sa_bb_wire = align_to_emax(sa_b_wire, sa_emax_wire);

end

// Stage sa0 — register the sign-extended aligned operands (before the adder).

logic signed [24:0] sa0_aa, sa0_bb;

logic [7:0] sa0_emax;

logic sa0_valid;

always_ff @(posedge clk_core or negedge rst_n_core) begin

if (!rst_n_core) begin

sa0_aa <= '0;

sa0_bb <= '0;

sa0_emax <= '0;

sa0_valid <= 1'b0;

end else if (ce) begin

sa0_valid <= in_valid_s0;

sa0_aa <= $signed({sa_a_wire.sign, sa_aa_wire});

sa0_bb <= $signed({sa_b_wire.sign, sa_bb_wire});

sa0_emax <= sa_emax_wire;

end

07 PERF

Perf chart B

4 metrics · 4 rows · 0 notes

Lower MAC util with heavier DMA write share

Interpretation

The Perf section reviews performance samples and utilization trends. It reorganizes 4 metric(s), 0 detail row(s), and 0 note(s) from the “Perf chart B” artifact into report form.

The first observation is MAC avg = 44.2%. This value should be read against the neighboring metrics in the same artifact; the current flagged metric count is 2.

The Perf section contains warning-level signals. Use the 2 flagged metric(s) to trace cause and scope.

Evidence basis

This section summarizes 4 evidence item(s). The representative metric is MAC avg = 44.2%, and source path is analyze/altifigence-npu-full-v003/perf.json. The interpretation is linked to stored analysis output.

The “Perf chart B” result in Perf required additional review. Compare MAC avg = 44.2% against neighboring artifacts and inspect the detailed path in the full viewer.

GRAPH

Interactive preview · Sample data · Select a tab to explore.

<40s

Fast AST indexing¹

Incremental parsing of large RTL codebases and modules with millions of lines in under 40 seconds

100%

Syntax conformance²

Full compatibility with the IEEE 1800-2017 SystemVerilog standard and Sail formal specifications

10x

Shorter verification cycles³

Reduce debugging cycles with automatic DRC and CDC analysis before synthesis

Zero

Open interfaces without lock-in⁴

Connect existing pipelines through MCP and the CLI

Your preferred AI. Your familiar design tools.

AI model integrations⁵

Supported technologies and tools⁵

Open-source hardware designed with Altifigence⁶

An open-source hardware reference project synthesized and verified with the Altifigence toolchain.

PCCX.ai Project documentation GitHub

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¹AST performance measurement environment and scope
“Under 40 seconds” refers to the incremental AST update time when Digital Design Studio processes a predefined RTL change to the PCCX v002 project in a cloud environment with 8 virtual CPUs, 32 GiB of memory, and Ubuntu 24.04 LTS. The figure is based on the median of 30 measurements taken from the same initial state and under the same change conditions, after initial analysis and 3 warm-up runs. It excludes the initial full analysis, project upload, and network transfer time. Actual processing time may vary depending on project structure, the extent of the changes, cache state, and server resources.
²Test pass rate and language support scope
“100%” is the proportion of all designated test cases that met their expected results in a predefined SystemVerilog syntax regression test suite based on the PCCX v002 project, using the Digital Design Studio build under measurement. Failed or skipped test cases are not counted as passes. This figure applies only to the specified test scope and does not indicate compliance with the entire SystemVerilog standard, the accuracy of simulation or synthesis results, or full compatibility with third-party tools. Sail support and validation are not included in this figure.
³Comparison baseline and performance measurement method
“Up to 10×” is the result of comparing validation feedback times for full reanalysis and incremental analysis, using predefined change scenarios for the PCCX v002 project in the same cloud environment and Digital Design Studio build. Both methods use the same DRC and CDC check scope and assessment criteria. For each method, the median elapsed time is calculated from 30 measurements after 3 warm-up runs. The ratio is the median full reanalysis time divided by the median incremental analysis time, and the reported figure is the highest ratio among the predefined scenarios. It does not imply the same reduction in the overall design and verification cycle. Actual results may vary depending on design characteristics and the execution environment.
⁴Scope of interface integration
“Openness” means that Digital Design Studio can connect to external tools and automation pipelines through its MCP interface and CLI commands. Available functionality and integration scope may vary depending on the product version, the configuration of the integration target, access permissions, and license terms. It does not mean that the entire product is open source or that it is compatible with every external tool.
⁵Trademark and license notice
Rights to the third-party names and logos shown belong to their respective rights holders. They are displayed to identify supported technologies and integration targets and, unless otherwise stated, do not imply a partnership, sponsorship, certification, or guarantee relationship between those companies or organizations and Altifigence. Use of each technology and tool is subject to the licenses and terms of use set by its respective rights holder.
⁶Terms for using open-source hardware
Use of publicly available source related to PCCX v002 is subject to the licenses and notices in the relevant repository. The linked KV260 integration project repository is licensed under the Apache License 2.0; where a separate license is specified for an individual file or external component, those terms apply. For materials such as documentation and images, consult the license applicable to each item. Permission to use publicly available source does not also grant permission to use trademarks such as names or logos.